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CY62146EV30 MoBL(R)
4-Mbit (256K x 16) Static RAM
Features
* Very high speed: 45 ns * Wide voltage range: 2.20V-3.60V * Pin compatible with CY62146DV30 * Ultra low standby power -- Typical standby current: 1 A -- Maximum standby current: 7 A * Ultra low active power -- Typical active current: 2 mA @ f = 1 MHz * Easy memory expansion with CE, and OE features * Automatic power down when deselected * CMOS for optimum speed and power * Available in a Pb-free 48-ball VFBGA and 44-pin TSOP II packages reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: * Deselected (CE HIGH) * Outputs are disabled (OE HIGH) * Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) * Write operation is active (CE LOW and WE LOW) Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A17). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the "Truth Table" on page 9 for a complete description of read and write modes.
Functional Description [1]
The CY62146EV30 is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly
Product Portfolio
Power Dissipation Product VCC Range (V) Min CY62146EV30LL 2.2 Typ [2] 3.0 Max 3.6 45 ns Speed (ns) Typ [2] 2 Operating ICC (mA) f = 1 MHz Max 2.5 f = fmax Typ [2] 15 Max 20 Standby ISB2 (A) Typ [2] 1 Max 7
Notes: 1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C.
Cypress Semiconductor Corporation Document #: 38-05567 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 26, 2007
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CY62146EV30 MoBL(R)
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
256K x 16 RAM Array
SENSE AMPS
IO0-IO7 IO8-IO15
COLUMN DECODER
BHE WE CE OE BLE
A11
A12
A13
A15
A14
Pin Configurations [3, 4]
48-ball VFBGA Top View
1 BLE IO8 IO9 VSS VCC IO14 IO15 NC 2 OE BHE IO10 IO11 IO12 IO13 NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE IO1 IO3 IO4 IO5 WE A11 6 NC IO0 IO2 VCC VSS IO6 IO7 NC A B C D E F G H A4 A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A17 A16 A15 A14 A13
A16
A17
44-pin TSOP II Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 NC A8 A9 A10 A11 A12
Notes: 3. NC pins are not connected on the die. 4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb and 32 Mb, respectively.
Document #: 38-05567 Rev. *C
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CY62146EV30 MoBL(R)
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied ........................................... -55C to + 125C Supply Voltage to Ground Potential .............................-0.3V to + 3.9V (VCCmax + 0.3V) DC Voltage Applied to Outputs in High-Z State [5, 6] ................-0.3V to 3.9V (VCCmax + 0.3V) DC Input Voltage [5, 6] ........... -0.3V to 3.9V (VCC max + 0.3V) Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ......................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current ..................................................... >200 mA
Operating Range
Device CY62146EV30 Range Industrial Ambient Temperature VCC [7]
-40C to +85C 2.2V to 3.6V
Electrical Characteristics (Over the Operating Range)
45 ns Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Test Conditions IOH = -0.1 mA IOH = -1.0 mA, VCC > 2.70V Output LOW Voltage IOL = 0.1 mA IOL = 2.1 mA, VCC > 2.70V Input HIGH Voltage VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V Input LOW Voltage VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V Input Leakage Current Output Leakage Current GND < VI < VCC GND < VO < VCC, Output Disabled f = 1 MHz ISB1 Automatic CE Power down Current -- CMOS Inputs VCC = VCC(max), IOUT = 0 mA CMOS levels 1.8 2.2 -0.3 -0.3 -1 -1 15 2 1 Min 2.0 2.4 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +1 20 2.5 7 A Typ [2] Max Unit V V V V V V V V A A mA
VCC Operating Supply Current f = fmax = 1/tRC
CE > VCC-0.2V, VIN > VCC-0.2V or VIN < 0.2V f = fmax (Address and Data Only), f = 0 (OE, BHE, BLE and WE), VCC = 3.60V
ISB2 [8]
Automatic CE Power down Current -- CMOS Inputs
CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V
1
7
A
Notes: 5. VIL(min) = -2.0V for pulse durations less than 20 ns. 6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 7. Full device AC operation assumes a minimum of 100 s ramp time from 0 to Vcc(min) and 200 s wait time after Vcc stabilization. 8. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document #: 38-05567 Rev. *C
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CY62146EV30 MoBL(R)
Capacitance (For All Packages) [9]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Thermal Resistance [9]
Parameter JA JC Description Test Conditions VFBGA Package 75 10 TSOP II Package 77 13 Unit C/W C/W
Thermal Resistance Still Air, soldered on a 3 x 4.5 inch, (Junction to Ambient) two-layer printed circuit board Thermal Resistance (Junction to Case)
AC Test Loads and Waveforms
VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 R1 VCC 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT OUTPUT RTH V 3.0V 1103 1554 645 1.75 Unit V
Parameters R1 R2 RTH VTH
2.50V 16667 15385 8000 1.20
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR
[8]
Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Conditions VCC = 1.5V, CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V
Min 1.5
Typ [2] 0.8
Max 7
Unit V A ns ns
tCDR [9] tR
[10]
0 tRC
Data Retention Waveform
DATA RETENTION MODE VCC CE
VCC(min)
tCDR
VDR > 1.5V
VCC(min)
tR
Notes: 9. Tested initially and after any design or process changes that may affect these parameters. 10. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
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CY62146EV30 MoBL(R)
Switching Characteristics (Over the Operating Range) [11, 12]
45 ns Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE
[15]
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z CE LOW to Low-Z
[13] [13, 14]
Min 45
Max
Unit ns
45 10 45 22 5 18 10 18 0 45 22 5 18 45 35 35 0 0 35 35 25 0 18 10
[13] [13, 14]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High-Z CE HIGH to High-Z
[13] [13, 14]
CE LOW to Power Up CE HIGH to Power Down BLE / BHE LOW to Data Valid BLE / BHE LOW to Low-Z BLE / BHE HIGH to High-Z Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BLE / BHE LOW to Write End Data Setup to Write End Data Hold from Write End WE LOW to High-Z WE HIGH to Low-Z
[13, 14] [13]
Notes: 11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" on page 4. 12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state. 15. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 38-05567 Rev. *C
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CY62146EV30 MoBL(R)
Switching Waveforms
Read Cycle 1 (Address Transition Controlled) [16, 17]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled) [17, 18]
ADDRESS
tRC CE tACE OE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB DATA VALID HIGH IMPEDANCE tHZOE tPD tHZCE
Notes: 16. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 17. WE is HIGH for read cycle. 18. Address valid before or similar to CE and BHE, BLE transition LOW.
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CY62146EV30 MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled) [15, 19, 20]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
BHE/BLE
tBW
OE DATA IO NOTE 21 tHZOE
tSD DATAIN
tHD
Write Cycle No. 2 (CE Controlled) [15, 19, 20]
tWC ADDRESS tSCE CE
tSA
WE
tAW tPWE
tHA
BHE/BLE
tBW
OE tSD DATA IO NOTE 21 tHZOE DATAIN tHD
Notes: 19. Data IO is high impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 21. During this period, the IOs are in output state and input signals must not be applied.
Document #: 38-05567 Rev. *C
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CY62146EV30 MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW) [20]
tWC ADDRESS tSCE CE
BHE/BLE tAW WE tSA
tBW tHA tPWE
tSD DATA IO NOTE 21 tHZWE DATAIN
tHD
tLZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [20]
tWC ADDRESS
CE tSCE
tAW BHE/BLE tSA WE
tHZWE
tHA tBW
tPWE tSD DATAIN
tLZWE
tHD
DATA IO
NOTE 21
Document #: 38-05567 Rev. *C
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CY62146EV30 MoBL(R)
Truth Table
CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High-Z High-Z Data Out (IO0-IO15) Data Out (IO0-IO7); IO8-IO15 in High-Z Data Out (IO8-IO15); IO0-IO7 in High-Z High-Z High-Z High-Z Data In (IO0-IO15) Data In (IO0-IO7); IO8-IO15 in High-Z Data In (IO8-IO15); IO0-IO7 in High-Z Mode Deselect/Power down Output Disabled Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 45 Ordering Code CY62146EV30LL-45BVXI CY62146EV30LL-45ZSXI Package Diagram Package Type Operating Range Industrial
51-85150 48-ball VFBGA (Pb-free) 51-85087 44-pin TSOP II (Pb-free)
Please contact your local Cypress sales representative for availability of other parts
Document #: 38-05567 Rev. *C
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CY62146EV30 MoBL(R)
Package Diagrams
Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150
TOP VIEW BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C 1.00 MAX
SEATING PLANE 0.26 MAX. C
51-85150-*D
Document #: 38-05567 Rev. *C
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CY62146EV30 MoBL(R)
Package Diagrams (continued)
Figure 2. 44-pin TSOP II, 51-85087
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05567 Rev. *C
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(c) Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62146EV30 MoBL(R)
Document History Page
Document Title:CY62146EV30 MoBL(R), 4-Mbit (256K x 16) Static RAM Document Number: 38-05567 REV. ** *A ECN NO. Issue Date 223225 247373 See ECN See ECN Orig. of Change AJU SYT New Data Sheet Changed Advance Information to Preliminary Moved Product Portfolio to Page 2 Changed VCC stabilization time in footnote #8 from 100 s to 200 s Removed Footnote #14(tLZBE) from Previous revision Changed ICCDR from 2.0 A to 2.5 A Changed typo in Data Retention Characteristics(tR) from 100 s to tRC ns Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Changed tDBE from 15 to 18 ns for 35 ns Speed Bin Changed Ordering Information to include Pb-Free Packages Changed from Preliminary information to Final Changed the address of Cypress Semiconductor Corporation on Page #1 from "3901 North First Street" to "198 Champion Court" Removed 35ns Speed Bin Removed "L" version of CY62146EV30 Changed ball E3 from DNU to NC Removed the redundant foot note on DNU. Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from 1.5 mA to 2 mA at f=1 MHz Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax Changed ISB1 and ISB2 Typ values from 0.7 A to 1 A and Max values from 2.5 A to 7 A. Changed the AC test load capacitance from 50pF to 30pF on Page# 4 Changed ICCDR from 2.5 A to 7 A. Added ICCDR typical value. Changed tLZOE from 3 ns to 5 ns Changed tLZCE and tLZWE from 6 ns to 10 ns Changed tLZBE from 6 ns to 5 ns Changed tHZCE from 22 ns to 18 ns Changed tPWE from 30 ns to 35 ns. Changed tSD from 22 ns to 25 ns. Updated the package diagram 48-ball VFBGA from *B to *D Updated the ordering information table and replaced the Package Name column with Package Diagram. Added footnote #8 related to ISB2 and ICCDR Added footnote #12 related AC timing parameters Description of Change
*B
414807
See ECN
ZSD
*C
925501
See ECN
VKN
Document #: 38-05567 Rev. *C
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